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Iterative decoding of parallel concatenated block codes

Titre	Iterative decoding of parallel concatenated block codes
Publication Type	Conference Paper
Year of Publication	2008
Authors	Belkasmi, M, Farchane, A
Conference Name	2008 INTERNATIONAL CONFERENCE ON COMPUTER AND COMMUNICATION ENGINEERING, VOLS 1-3
Publisher	Int Islam Univ Malaysia, Fac Engn
ISBN Number	978-1-4244-2357-6
Abstract	Parallel concatenated block (PCB) codes based on two systematic block codes and an interleaver are considered. In this study BCH codes are used as component codes. At the reception an iterative decoder using Chase-Pyndiah as Soft-in Soft-Out algorithm is designed. The effects of various component codes, interleaver size and pattern, and the number of iterations are investigated using simulations. The simulation results show that the slope of curves and coding gain are improved by increasing the number of iterations and/or the interleaver size. From the simulations we observe that the codes PCB based on BCH(127,106,7) and BCH(255,215,11) codes are respectively 1.7dB and 2.1 dB from Shannon limit.
DOI	10.1109/ICCCE.2008.4580602