VHDL design and FPGA implementation of a fully parallel BCH SISO decoder

TitreVHDL design and FPGA implementation of a fully parallel BCH SISO decoder
Publication TypeConference Paper
Year of Publication2010
AuthorsM. Haroussi, E, Chana, I, Belkasmi, M
Conference Name2010 5th International Symposium on I/V Communications and Mobile Networks, ISIVC 2010
URLhttps://www.scopus.com/inward/record.uri?eid=2-s2.0-78651477175&doi=10.1109%2fISVC.2010.5656415&partnerID=40&md5=4ef5d844fa95aea85bc6781b1524b50e
DOI10.1109/ISVC.2010.5656415
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