VHDL design and FPGA implementation of weighted majority logic decoders

TitreVHDL design and FPGA implementation of weighted majority logic decoders
Publication TypeConference Paper
Year of Publication2011
AuthorsM. Haroussi, E, Ayoub, F, Belkasmi, M
Conference NameInternational Conference on Multimedia Computing and Systems -Proceedings
URLhttps://www.scopus.com/inward/record.uri?eid=2-s2.0-79961233273&doi=10.1109%2fICMCS.2011.5945599&partnerID=40&md5=07df2e3fcbba980a7e899b84c1e869ff
DOI10.1109/ICMCS.2011.5945599
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